High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to increase access speed while reducing power consumption for semiconductor devices. As part of that effort to increase access speed, it may be desirable to include input receiver circuits having faster operation in input buffers for receiving address signals, command signals and clock signals. Simultaneously, it may be desirable to accommodate a wide range of input signals at the input receiver circuits to meet recent semiconductor devices (e.g., low-power double data rate synchronous DRAM). For example, Low Power Double Data Rate 4 (LPDDR4) specification (JESD209-4) specifies that a data input reference voltage (VREF) operating point range from 10 % to 42 % of a power supply voltage for data input (VDD). Along these lines, an input receiver circuit including differential amplifiers have been developed. For example, a data latch type input buffer has been used as an input buffer for memory devices (e.g., LPDDR4). A data latch type input (DQ) buffer in a memory device amplifies a data signal and latches the data signal by amplifying a voltage difference between the data input signal and the VREF when a clock signal CLK is at a logic high level, and initializes each node in the DQ buffer by precharging each node when the clock signal CLK is at a logic low level. The DQ input buffer performs a sequence of amplification and latch operation responsive to a signal input and a precharge operation in turn during each clock cycle. Source nodes of input transistors may receive a power supply voltage VDD and gate nodes of the input transistors coupled to input nodes (IN+ node and IN− node) may receive a data input signal DQ and the reference voltage VREF, respectively while performing the sequence of amplification and latch operation. However, the input transistors may not be driven fast enough due to a smaller VGS of the input transistors M1 and M2, if a voltage of the data input signal DQ and the reference voltage VREF become higher (e.g., VREF=42%*VDD).
FIG. 1 is a circuit diagram of a conventional input buffer circuit. The conventional data input buffer circuit includes a first amplifier including transistors M1, M2, M3, M4, M5 and M6. A transistor M0 is a switch of the first amplifier. A data input signal DQ is provided to an IN+ node coupled to a gate of the transistor M1. The reference voltage VREF is provided to an IN− node coupled to a gate of the transistor M2. A sequence of amplification and latch operation are executed, when an inverted clock signal CLKB is at a logic low level that activates transistor M0 and deactivates transistors M7-M10. The power supply voltage VDD is provided to nodes, (node1 and node2) through transistors M1 and M2 and voltages of the nodes (node1 and node2) are increased from a precharge level VSS responsive to the inverted clock signal CLKB is at the logic low level, depending on the data input signal DQ. Thus, a voltage difference Vdiff between the nodes (node1 and node2) may be caused based on a difference between a voltage of the input data input signal DQ and the reference voltage VREF. Because the power supply voltage VDD is provided to nodes (node1 and node2), voltages at an OUT− node and an OUT+ node may be increased from the precharge level VSS through transistors M3 and M4 respectively, when the voltage difference Vdiff exceeds a threshold voltage VTh of the transistor M3 or a threshold voltage VTh of the transistor M4. Due to voltages of the node1 and the node2 that are increased up to approximately the power supply voltage VDD, the first amplifier latches a voltage difference between the OUT− node and the OUT+ node of the first amplifier, and a logic high level signal (VDD) is provided to one of the OUT− node and the OUT+ node and a logic low level signal (VSS) is provided to the other of the OUT− node and the OUT+ node. In a precharge operation, when the inverted clock signal CLKB is at a logic high level, the nodes node1, node2, OUT− and OUT+ are precharged by precharge transistors M7, M8, M9 and M10 to a logic low level signal (VSS). An increase of the voltage of the node1 above the threshold VTh of the transistor M3 drives capacitors (not shown) related to the transistor M1 and capacitors coupled to the OUT− node, (e.g., capacitors at gates of the transistors M4 and M6, a channel capacitor of the transistor M3 and a drain capacitor of the transistor M5), and a total capacitance of these capacitors is remarkably large. Similarly, a total capacitance of capacitors related to the transistor M2 is large. Accordingly, a time to increase voltages of the nodes (node1 and node2) around the power supply voltage VDD and to complete the sequence of amplification and latch operation to increase voltages at an OUT− node and an OUT+ node is longer when the data input signal DQ and the reference voltage VREF are higher, and the sequence of amplification and latch operation may not be completed by a precharge operation in the data input buffer circuit.
Besides, the data input buffer circuit of FIG. 1 has a problem that an input offset occurs due to mismatch between threshold voltages of paired transistors. For example, when a difference between a threshold voltage of the transistor M1 and a threshold voltage of the transistor M2 is caused by process variation, an operating point of the IN+ node is deviated from the reference voltage VREF. Also, when there is a difference between the threshold voltage of the transistor M3 and the threshold voltage of the transistor M4 or when there is a difference between a threshold voltage of the transistor M5 and a threshold voltage of the transistor M6, an input offset similarly occurs.
FIG. 2 is a circuit diagram of another conventional data input buffer circuit. The data input buffer circuit shown in FIG. 2 includes transistors M110 to M11m connected in parallel to the transistor M1, and transistors M120 to M12m connected in series to the transistors M110 to M11m, respectively. Gate electrodes of the transistors M1 and M110 to M11m are connected to the IN+ node in common. Corresponding bits of a first code signal CODE1 are provided to gate electrodes of the transistors M120 to M12m, respectively. Similarly, the data input buffer circuit shown in FIG. 2 includes transistors M130 to M13m connected in parallel to the transistor M2, and transistors M140 to M14m connected in series to the transistors M130 to M13m, respectively. Gate electrodes of the transistors M2 and M130 to M13m are connected to the IN− node in common. Corresponding bits of a second code signal CODE2 are provided to gate electrodes of the transistors to M140 to M14m, respectively. Accordingly, the capability of a transistor circuit MC1 can be adjusted based on a value of the code signal CODE1 and the capability of a transistor circuit MC2 can be adjusted based on a value of the code signal CODE2. Therefore, even when the threshold voltage of the transistor M1 and the threshold voltage of the transistor M2 mismatch with each other, an input offset caused by the mismatch can be cancelled.
The data input buffer circuit shown in FIG. 2 includes a flip-flop circuit including transistors M14, M15, M16, and M17. A transistor M26 is connected between a source of the transistor M16 and a VSS terminal. A gate electrode of the transistor M26 is connected to the node1. A transistor M27 is connected between a source of the transistor M17 and the VSS terminal. A gate electrode of the transistor M27 is connected to the node2. Accordingly, capacitance components of the node1 and the node2 are reduced relative to those in the data input buffer circuit shown in FIG. 1 and a faster operation can be realized. Transistors M28 and M29 are connected to the OUT+ node and the OUT− node, respectively, and the OUT+ node and the OUT− node are both precharged to a VDD level when the clock signal CLK is at a low level.
However, in the data input buffer circuit shown in FIG. 2, channel capacitors of the transistors M110 to M11m and M120 to M12m are added to the node1 and channel capacitors of the transistors M130 to M13m and M140 to M14m are added to the node2. These channel capacitors interrupt a much faster operation.